Peter Jamieson, Ph.D.

Portrait of Peter Jamieson

Associate Professor

260 N Garland Hall

Research Interests

  • Mobile Computing with FPGAs
  • Genetic Algorithms for Placement
  • Placement Improvement
  • Verilog Synthesis
  • Serious Games
  • Education


  • Ph.D., Computer Engineering
    University of Toronto
  • M.S., Computer Engineering
    University of Toronto
  • B.S., Computer Engineering
    University of Ottawa


  • Associate Professor, Miami University, 2015Present
  • Assistant Professor, Miami University, 20092015
  • Visiting Professor, The University of British Columbia, 2012
  • Visiting Professor, Simon Fraser University, 2012

Honors and Awards

  • 2015 Distinguished Teaching Award

Principle Publications

Book Chapters

  • "Gaming with Purpose: Heuristic Understanding of Ubiquitous Game Development and Design for Human Computation" Lindsay Grace and Peter Jamieson. IEEE Handbook of Digital Games (ISBN: 978-1-118-32803-3). Editors M. Angelides and H. Agius. Wiley-IEEE Press - 2014

Journal Articles

  • "Advancing genetic algorithm approaches to field programmable gate array placement with enhanced recombination operators" Robert Collier, Christian Fobel, Ryan Pattison, Gary Grewal, Shawki Areibi, and Peter Jamieson. Journal of Evolutionary Intelligence. October 2014.
  • "Analyzing System-Level Information's Correlation to FPGA Placement" Farnaz Gharibian, Lesley Shannon, Peter Jamieson, and Kevin Chung. ACM Transactions on Reconfigurable Technology and Systems. Vol. 6. Number 3. October 2013.
  • "Power consumption benchmarking for reconfigurable platforms". Teemu Pitkanen, Peter Jamieson, Tobias Becker, Sami Moisio, and Jarmo Takala. Analog Integrated Circuits and Signal Processing
  • "VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling". Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Mark Fang, and Jonathan Rose, ACM Transactions on Reconfigurable Technology and Systems. Vol. 4. Number 4. December 2011.
  • "Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters". Peter Jamieson and Jonathan Rose IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Vol. 18. Number 12, pp 1696 -1709, 2010